Digital logic circuit utilizing transformers



A ril 6, 1965 NORIYOSHI KUROYANAGI 3,177,371

DIGITAL LOGIC CIRCUIT UTILIZING TRANSFORMERS '7 Sheets-Sheet 1 Filed May 19, 1960 a? Q @g A il 6, 1965 NORIYOSHI KUROYANA GI 3,177,371

DIGITAL LOGIC CIRCUIT UTILIZING TRANSFORMERS Filed lay 19, 1960 7 Sheets-Sheet 2 a a a I INVENTOR. A/OE/VOSHI K120 r/uvncl. BY

xlrm/P/vfxr April 1965 NORIYOSH! KUROYANAGI 3,177,371

DIGITAL LOGIC CIRCUIT UTILIZING TRANSFORMERS Filed May 19. 1960 '7 Sheets-Sheet 3 Y T*-F I 1 HI. INVENTOR. k VOEQOSH/KJ/ZOY/INAGI.

1 p 6, 1955 NORIYOSHI KUROYANAGI 3,177,371

I DIGITAL LOGIC CIRCUIT UTILIZING TRANSFORMERS 1 Fild May 19,; 1960 7 Sheets-Sheet 6 S mm a a F i l O w mm 3 35 E3 RE 9\ ONE Mm NW N k $3 R 3Q Em at INVENTOR. A/O/P/VOSH/ [1 1/20 VAN/4G7.

7 Sheets-Sheet 7 Q g g \u I 1 a o M k E? E kfi N NORIYOSHI KUROYANAGI I BOO-l DIGITAL LOGIC CIRCUIT UTILIZING TRANSFORMERS April 6, 1965 Filed May 19, 1960 ATTO/F/VEYJI United States Patent 3,177,371 DIGITAL LOGIC CIRCUIT UTILIZING TRANSFORMERS Noriyoshi Kuroyanagi, Mitaka-shi, Japan, ass1gnor to Nippon Telegraph & Telephone Public Corporation, Tokyo, Japan, a corporation of Japan Filed May 19, 1960, Ser. No. 30,103 Claims priority, application Japan, May 25, 1959, 34/16,?132; Mar. 10, 1960, 35/7,706, 35/7,407, 35/7,408; Mar. 16, 1960, 35/8,282

7 Claims. (Cl. 307-885) The invention relates to a logical circuit. In high speed digital electric computers in larger scale, it is necessary to transmit whole numeral information stored in each of the resistors as one word of the number in an arithmetic unit as an information group consisting of one unit of a word to one of the other resistor groups or circuits. If an ordinary logical circuit of diodes is employed as selective transmission lines for this purpose, the number of elements increases considerably, and, its power etliciency being poor, it necessitates a long chain of stages of logical operation regeneration amplification. Therefore, it has a disadvantage of taking much time for this sort of selective transmission.

Though a logical operation of NOT is a necessary function for various kinds of control of an arithmetic circuit, its power efiiciency, when equipped with ordinary diode logical circuits, is not a satisfactory one and it makes a logical layout somewhat difiicult. Generally, the floating point system in the arithmetic calculation is superior to the fixed point system which has to be stopped every time when the overflows come out. The former can treat the numbers in larger scale than the latter. But, in the floating point'system', if an ordinary logical circuit is employed for it, it takes more time for the operation than with a fixed point device, and it takes even ten times the time of operation of the fixed point calculation system.

For the floating point system calculation, the number has to be analyzed in number part and index part, by which the binary point is assigned. In making an addition or subtraction of two numbers, these indexes are compared against each other at first, then the number part, the digit number of their diiference in absolute value is shifted, both number parts are added or subtracted, and the sum obtained by addition or subtraction is again shifted to get an exact binary point, so that the right index part can be obtained. In the arithmetic units hitherto known, the shifting is performed by the repetition of each hit one by one, checking the shifted times against the shifting counter. It takes therefore the operation time of one step for the shifting of each bit of the digit and a long time is required for operation, when the number of digits to be shifted increases.

The present invention aims to remove such substantial defects which the usual logical circuit and logical system have, and it offers a new circuit with some improvement in the selective transmission line, a logical NOT circuit and a high speed shifting circuit. It provides the rent in the'load impedance inserted intoa part of said branch line, connecting the gate elements, the conduction of which is controlled by the input, and the voltage feeder "ice that has the inducing voltage is controlled by one of the inputs.

In the following the invention will be explained in detail referring to the drawings, wherein:

FIG. 1 shows a basic circuit according to the idea of the invention.

FIG. 2 shows a logical circuit of an example constructed on the principle of FIG. 1.

FIG. 3 shows a circuit of the left half of that of FIG. 2.

FIG. 4 shows selective transmission lines which connect the resistors and the arithmetic circuit to each other.

FIG. 5 shows another basic circuit after the invention.

FIG. 6 shows a logical circuit of an example constructed in accordance with the principle shown in FIG. 5.

FIG. .7 shows still another example of basic circuit with the same function as aforementioned circuits according to the invention.

FIG. 8 shows the logical circuit of an embodiment constructed in conformity with the principle of FIG. 7.

FIG. 9 is another example of the circuit to which the principle of FIG. 7 is applied.

FIG. 10 shows a block diagram of a circuit which is an example of the invention.

FIG. 11 shows the wiring of the circuits used in the example in FIG. 10.

FIG. 12 shows another circuit used as gate in FIG. 11.

FIG. 13 shows a block diagram of a variation of the example illustrated in FIG. 10.

FIG. 14 shows a connection of the circuits employed in the example of FIG. 13.

Referring to FIG. 1, the reference letter or symbol H designates a transistor, L, a conventional, polarity insensitive pulse transformer, R, a load resistor, x and y, the input terminals to be driven by the signal inputs corresponding to the input logical values 2: and y respectively, and u, the output terminal which similarly corresponds to the logical value U.

The symbols in the figures of the drawings are so employed that the part or parts having the same function are denoted by the same symbols, but sometimes sufiixes are attached in order to avoid confusion when there are a plurality of the same parts which have to be distinguished from one another in a figure. v is used as the symbol to show an indefinite number but not including 0.

The input in FIG. 1 is applied to terminal at and the emitter current flows into the transistor H which is in a conductive state only for the length of time the input pulse exists. When a voltage is not applied to the collector, collector current is not produced, but if a negative voltage, which is induced through the transformer L when input is applied to y, is supplied to the collector, the collector current flows.

Consequently, if the inputs are applied to x and y simultaneously (both input pulses should overlap at least part of the time), the current fiows in the arrow direction and a positive output appears at u. But, if an input for example x the junction point M gets then into a conductive state to the earth through the transistor H into which the emitter current flows. When the input is applied also to y the voltagein the arrow direction is induced within the secondary winding of L I resistors or arithmetic'circuit.

V sponding small cellof'th e adder.

terminals when the inputs are not applied to any of the y even when an input signal is applied to an x terminal. a

The logical function of this circuit is:

which is a logical sum or OR circuit.

If the inputs for X =Y ==1 are applied to it, the current flows into the path p in accordance with said principle. If the forward resistance of d be smaller than R and if sufficient currentie flows into the emitter of the transistor H the power given to y will appear at the load resistance R without any large attenuation. On the other hand, if asufiicient input is applied to y, the collector current aie will flow intothe path p. almost freefrom attenuation. 1 1

In consequence, this circuit has, theoretically, a high efficiency. Moreover, if the ordinary impedance for y and the load resistance R are in proper balance and if a sufficient amount of emitter current is provided, a more effective circuit for input y is obtained. The input im- When the synchronizing and reshaping inputs are con-Y j nected to drive y and there is a minute diiference regarding the time and power level, the output that appears at I u will be offset, and thus, the function of y also can be replaced by x 'and the input for x can be employed as a synchronizing and reshaping factor. this arrangement, the transistors are used with base ground circuits, but an almostsame result can be achieved by diodes are employed in place of the transistors in FIG. 2. Here the diodes d are used as gate elements, and C In an example of using them, for example, with emitter ground circuits. In FIG. 3 another embodiment ofa circuit and having gate elements is illustrated. 'In the circuit of FIG. 3,

designates a condenser, Re, a leak resistor, and R, a coupling. resistor; A positive or negative bias voltage V corresponding to the binary values of the outputs of flipfiop circuits F F and F are applied to diodes d which perform a gate function. y

FIG. 4 shows an example ofa circuit configuration in I sistsof a number'of circuits, one for each bit. The small it is desired totransrnit all information in two resistors Q and Q to the adder Q simultaneously, the information of each bit in the smallcell of ,resistor'reaches the corre- For simplicity sake, onlyLSB will be taken up in this case. The information for LSB in Q will be transmitted through'the path P to the small cell for'the'LSB in the adder, and theinformation for LSB in Q; will go through the path P5 like are the Each one of them con-' output transformer, n and 11 two primary windingsiand n thesecondary winding of T-. ,If the'emitter circuit wise. P and P are shown by dotted lines in FIG; 4. M and M correspond to the M in the FIG. '3 and the selective transmission lines to and-from the distributors are composed of the left and right part of the circuit illustrated in FIG. 2 p

Since all information. of a number, which consists of 11 bits and are treated as one word, have to be transmitted at one time in the arithmetic unit of a parallel computer, the high efiiciency selective transmission circuits are to include pulse-transformers with one primary winding and some portions of 'the secondary winding. The trans formers perform the same function as L in FIG."2.

Another basic circuit according to -the invention is shown in FIG. 5, wherein E designates a terminal connected to a negativedirect voltage source, H designates a transistor, L,.a pulse-transformen'R, a load resistor, R1, a resistor, C, a'condenser, d, a diode,'x and y, input terminals, and u, an output terminal. I

The base direct current flows always into H and H is in the state in which the collector current canvflow with negative collector voltage; In consequence, if an input signal is applied toy, and a voltage in the arrow direction is induced, the collector current fiows only for the time of the pulse andthe output will be obtained atiterminal it. But, if a positive input is put to x, the basevoltage of H will be kept'at a positive potential for a short time 7 by means of the storage functionof condenser C. Therefore, even if the input is applied toy, whenthe base voltage is kept positive no output signal appears because H is in a non-conductive state. This base positive voltage discharges at the time constant to be determined by con 'denser C and resistor R1, and the base direct current flows in the transistor H again after C'discharges. If such time constant is not required, condenser C can be omitted.

If a, suificient base current is passed. into transistor H, when the input is not applied to x, andthe aforementioned balance, between the driving impedance of y and the load resistance is made, the high 'eificiency denial circuit can be constructed inv conformity with in connection with'FIG. 2.

Another embodiment of a 'logicakcircuit comprising the basic circuit ofFIG. 5 is'shown'in FIG. 6. If in FIG.

6 the logical input signals correspond. to X X =Y =1,

v making all others 0, the current flows along the path p and a the output is obtained at 11 in accordance with the aforementioned principle. Thus the -logical func tion of this cireuitiszr i a Uu=(- +X +X )Yu I wherezt=l,2,3., I

Another basic circuit according to the invention is shown in' FIG. 7." x, xdesignate a pairof'the input terminals corresponding to the logical value of X, T,an

current ie from x, x flows into transistor H, an output willibe obtained at it through T. When an input signal. is not applied to y, the collector current does not how.

' Then, if the input signal is put to x,- x and y, the currents in and ic flow simultaneously and these-two currents set-off will not 'beperfect, For the .purposefof removing thisdisadvantage, the number. of windiugsi of T through will counteract at the base region, and no output- Will. be obtained. Generally, since iC=Oti and 1, the above which is and-"ic'flow are fixed byn; and (rm-Hi respectively as his shown lIIFIGiT When/the inputsignal is applied to y only, currentsi'e audit; will not be induced the principles explained and therefore do not flow. The logical function of the circuit of FIG. 7 is:

U=X.'r.

If X is a constant input, then An example of a logical circuit based on the basic circuit of FIG. 7 is shown in FIG. 8. The collector of the transistor H is branched to three output terminals. The collector voltage is then given to all branches by means of the input for y that corresponds to the logical values of Y Y Y respectively.

The logical function of this circuit is as follows:

Diodes d are arranged in the branches to prevent the flowing of the inverse current.

An embodiment of the logical circuit to which the basic circuit of FIG. 7 is applied, is shown in FIG. 9; This circuit (carry propagating circuit) detects the extent of the carrying action in the case of addition and comprises the series and parallel connections of the transistors which are used as gate elements. In this circuit T T and T are the output transformers corresponding to T in FIG. 7.

In FIG. 9 the part enclosed with dotted line is a unit of the circuit for one bit. The carry propagating circuit for a number of bits comprises the cascade connection of this circuit. The input for C, and S, and are applied to the terminals C,(S,.o',), and (3,5,) respectively, and the corresponding transistors are turned into a conductive state or held in a non-conductive state with their input pulse values. V

' The logical function of the output. obtained at u, is expressed with a logical value U, as the following:

shift the binary number of 11 bits denoted by 'X,2, as manyas from 0 to m bits. 605,) is the gat element corresponding to each bit X. Here G represents the gate element and means 1, 2, 3 ..n. M, is the distributor controlled -by.G-(X,). V(y.n) where ,u. means m is the voltage feeder which corresponds to [.L bits for the shifting of X. T, is the am output transformer, A being v'r,u.. The both ends of the primary winding of the output transformer inserted in the branch line B0141.) are coupled to the voltage feeder V(y.

,coming from the distributor Mu are indicated with v.,Lb

and. (v. The upper end 1 .1w of the primary winding is to be coupled to the lower end 140 of B(v. ,u.) and the lower end (11.,u) of the primary winding tothe upper end (v.

ofB(1/.,u) in the FIG. 10.

Even when V (y. is driven and the negative voltage issupplied to each branch line which connects V(y.;t),

the current does not flow into any of the branch lines, if all the gates are kept in a non-conductive state. But, if

G(X,) is driven by the input and changed to the con- 5 ductive state, M, will conduct to the earth line and the current will flow to the branch line B(v.,u.) going to V(y.,u) from M,, Thus, the output is obtained through the output transformer T(v+p.) situated on B(1 .p.). And v if all gates are driven, the output will be obtained through each respective output transformer T(2+,u) T(n+ In any case, the current does not flow through more than two primary windings of the same transformer. Since there exist not more than two bits of numbers which correspond to the shifting bit at the same time, one of V(y. is driven only at a certain instant. Consequently, since the presence or absence of the. input which drives the am gate decides the presence or absence of (v+p.)th output, when V(y.;.t) is driven, the input information train of one sequence (X X X appears at the output terminals shifted by bits (U U U Still another example of a shifting circuit composed of the circuit in FIG. 10 is shown in FIG. 11, where H is the gate element G(X,), R and R are resistances, Eb

is the positive direct bias voltage.

Now, when the inputs are given to x and y, at the same time, the emitter current flows into the uppermost transistor H and the base current flows into the ,uth transistor H and M willtend to earth potential, the terminals p y, t (2;/.)', (1a) will tend to E. Thus the branch line which connects M and one of those terminals is the only Buy.) and it goes into the pulse transformer T(1+[.L) through which the output is obtained at the output terminal u(1+,u). Since this terminal acts likewise for the inputs to the other gates G(X,), the output appears generally at u(u+n).

In this way, the logical input will be shifted by ,u. bits simultaneously. The diodes are inserted for the purpose of preventing the flow of the inverse currents in the branch lines. R s are high resistances. They keep the distributors in a deep negative voltage by means of E and the circuit of R and -E keep the minute leakage current away which flows into the branch lines to the non-driven voltagefeeder. Furthermore, M, which is coupled to the gate in a conductive state approaches the earth potential and helps the flow ofthe minute leakage current into the branch lines which tend to flow in the non-driven voltage feeder.

The undesirable effects are removed through the insertion of R a low resistance between gates and distributors, because M,, in a conductive state too, is kept in a little lower potential than the earth. FIG. 12 illustrates a circuit corresponding to the left part of the circuit in FIG. 11. In this example, flip-flops F, are used as gate elements G(x,) of FIG. 10. The output terminal of F, becomes either potential 0 or c with the input logical value 1 or 0 or X.

If eEE then M, becomes conductivefor 0 and non-. conductive for -e by the action of. diode d.

A flip-flop circuit can be also employed as V(y.;r) in FIG. 10. In this case, the output terminal of the flip-flop becomes either potential e or 0 with the input logical value 1 or 0 for Y,,.

Furthermore, H can be used also as an emitter grounded connection and H as a base grounded connection. Another example of the block diagram according to the invention is shown in FIG. 13. This circuit has the same function as that of FIG. 10. But the location of the voltage feeder in this circuit is different from that of FIG. 10, and the pulse transformers as the output elements are not necessary except as the voltage feeder V(y.

The lower end up of VOL t) and the upper end up. of the output terminal Ll, ()\=1/+,u.) have to be coupled together.

Now, if the input for X,=1. and Y,=l are applied, as M,, connected to G(X,), tends to the conductive state and the voltage is induced between both ends of V(y. the current flows into the branch line that connects M,

and V(y.,u.) and theoutput is obtained at the outputterminal u,()\:v+,u.). In other'words, the relative posi- '2' tive positions of V(y. and the load resistances are reversed in the circuits of FIGS. and 13.

' A further example of the shifting circuit which is arranged after the block diagram in FIG. 13 is shownin FIG. 14, wherein L is a pulse transformer and is used as voltage feeder V(y.,a). winding of L, by the input to y,,, the voltage is induced in a number of parts of the secondary windings which connect alldistributors M,. Diode ds check the inverse current flow into the branch lines and perform the OR function by which each branch line corresponding to the same output terminal, is connected.

These shifting circuits can be applied not only to the binary numbers, but'also to decimal numbers or others which are codes by n bits, by the same principle.

For example, if a decimalnumber is represented by the excess of three codes, the value of each decimal digit X,, is expressed by bits X61, X52, X, and X If the circuit of FIG. 14 is considered, the distributors for X6! Xs+1 am arranged y NIH, M62, B463: M54, el-1a M542 and four distributors have to be arranged for each decimal digit which branch to the four parts of the secondary windings of the same transformer L, and these four branches are led to the respective output terminals a u u and u \=v+,u. Thus, the shifting circuit for the decimal number-will be formedl These tWo ;shifting-circuits can be applied as circuits to get the AND outputs for. each two bits of the two binary numbers. In this case, taking the circuit of FIG. 14 for example, all diodes connected to the output terminals are separated and led to the different output terminals respectively. Thus, the n pieces of AND outputs are obtained from the two numbers withn bits.

From the explanations above described, the features of the invention are summarized as follows:

(1) The logicalcircuit after the invention can be con structed with stable and cheap elements such as diodes, transistors and pulse transformers,

(2) Complicated logical functions can be solved by a smaller elements in comparison to other types of circuit and it enables a manufacturing of transformers with a number of windings, V

(3) The logical circuits after the. invention-have advantages in power efficiency, and less time is required than for regenerative amplification in performing complicated logical functions and in consequence, a high speed'operatio'n is possible with this type of circuit,

Since H drives theprimary (4) These circuits are applicable also to the high frequency region,

(5) Regarding the principal, applications and engineering of this type of circuits, it can be said:

a. in arithmetic equipment, the selective transmission are easy to construct. v V b. logical denial circuits with high efficiency, necessary 1 for various kinds of logical operation can be COD-1 structed as applications of the idea of this invention.

it is intended that all matters contained in the above descripiton or shown in the accompanying drawings shall be interpreted as illustrative and not in a limiting sense.

What is claimed is:

, circuits that transmit the information of one word, a

could be made in the above con-- struction and many different embodiments of this invention could be made without departing from the scope thereof,

of said second Winding, and voltagepulse supply means connected betwe'en 'said first and second electrodes for.

supplying a second control signal voltage pulse to said first and'second electrodes,said" voltage pulse being of a polarity and amplitude which will cause current to flow through said secondary Winding only when said second control signal voltage pulse is also supplied to said first and second electrodes and they bias on said third electrode otherwise being such that current flow through said secondary'winding substantially zero in the absence of. said first control signal and in the presence and absence a of said second control signal voltage pulse.

2. A logical circuit according to claim-l whereinsaid second control signal is a direct current biasing voltage and further comprises a pulse signal sourceconnected between said first and second electrodes and oppositely polarized with respect to said biasing voltage;

3. A logical circuit comprising agate control device having first, second and third electrodes, a first transformer having vprimary and secondarywindings, a secondtransformer having a pairvof' primary windings and a secondary winding, a load circuit connected :to' said I said pair of primary windings for supplying a second;

varying amplitude control signal to said fir'stand second electrodes, the ratio of the turns ofsaid pair of primary windings being such that the current in said load circuit is substantially zero during the simultaneous application of both said control signals to said device.

4. Alogical circuit according to claim 3 wherein said device is a transistor and said first, second and third elec trodes are respectively emitter, base. and collector electrodes.

5. t A logical circuit comprising a plurality of gate control devices, each of said devicesihavin g first, second and third electrodes, means interconnecting the third electrode of each device with a common point, a plurality of load circuits equal in n'umber to the number of said'devices, a plurality of transformers and uni-directional elements equal in number to the number of said devices, each of said transformers having a primary and afsecondary winding, means connecting the secondary winding" of each transformer and one of said elements in series with each other between said commonpointand one of said load circuits, meansconnected to the primary windings of said transformers for supplying first varying amplitude control signals thereto and thereby producing voltages at the outputs of the secondary windings, means connected to the first and second electrodes vof said devices for supplying second varying amplitude control signals thereto, saidvoltages being of a polarity and amplitude which will cause current to flow in'the. load circuit connected to the secondary windingattwhich a volt- 1." A logical circuitcomprising a gate control device having first, second and third electrodes, a transformer having primaryand secondary windings, means connect- 7 and another :of said electrodes, rneans for supplying a 'ing said secondary Winding between said third electrode age is produced only when said second controlsignals are also supplied to said first and second electrodes of at least one said device and the biason said third electrodes otherwise being such that current flow through aload circuit connected with a secondary winding issubstantially zero in the absence of first control signals at the primary winding associatedwith said last-mentioned sec- I ondary winding andin the presence" and absence of said second control signals. v i

' 6. A logical circuit comprising a plurality of gate con: trol devices, eachtqf said devices having'first, second 1 and third electrodes, means interconnecting the third electrode of each device With aflcomrnon point, a-plurality of said load circuits, means connected to the primary windings of said transformers for supplying first varying amplitude control signals thereto and thereby producing voltages at the outputs of the secondary windings, means for supplying a biasing voltage to each of said first and second electrodes, means connected to the first and second electrodes of said devices for supplying second varying amplitude control signals thereto, said voltages at the outputs of said secondary windings and said biasing voltage being of a polarity and amplitude which will cause current to flow in the load circuit connected to the secondary winding at which a voltage is produced only when said second control signals are absent at all said first and second electrodes and the bias on said electrodes otherwise being such that current flow through a load circuit connected with a secondary winding is substantially zero in the absence of first control signals at the primary winding associated with said last-mentioned secondary winding and in the presence and absence of said second control signals.

7. A logical circuit comprising a gate control device having first, second and third electrodes, a plurality of first transformers and uni-directional elements, each of said transformers having a primary and a secondary winding, means connecting the secondary winding of each transformer and one of said elements in series With each other between said third electrode and a common point, means connected to the primary windings of said transformers for supplying first varying amplitude con- 18 trol signals thereto and thereby producing voltages at the outputs of the secondary windings, a second transformer having a pair of primary windings connected in series between said second electrode and said common point and having a secondary Winding, a load circuit connected to said secondary winding, means connected to said first electrode and the junction point of said primary windings for supplying second varying amplitude control signals thereto, said voltages being of a polarity and amplitude which will cause current to flow in the secondary winding at which a voltage is produced only when said second control signals are also supplied to said first and second electrodes and the bias on said electrodes otherwise being such that current flow through said primary windings is substantially zero in the absence-of said second control signals, the ratio of the turns of said primary windings being such that the current in said load circuit is substantially zero when said first and second control signals are supplied simultaneously to a primary winding of a first transformer and to said first electrode.

References Cited by the Examiner UNITED STATES PATENTS ARTHUR GAUSS, Primary Examiner.

GEORGE N. WESTBY, Examiner. 

1. A LOGICAL CIRCUIT COMPRISING A GATE CONTROL DEVICE HAVING FIRST, SECOND AND THIRD ELECTRODES, A TRANSFORMER HAVING PRIMARY AND SECONDARY WINDINGS, MEANS CONNECTING SAID SECONDARY WINDING BETWEEN SAID THIRD ELECTRODE AND ANOTHER OF SAID ELECTRODES, MEANS FOR SUPPLYING A FIRST VARYING AMPLITUDE CONTROL SIGNAL TO SAID PRIMARY WINDING AND THEREBY PROVIDING A VOLTAGE AT THE OUTPUT OF SAID SECOND WINDING, AND VOLTAGE PULSE SUPPLY MEANS CONNECTED BETWEEN SAID FIRST AND SECOND ELECTRODES FOR SUPPLYING A SECOND CONTROL SIGNAL VOLTAGE PULSE TO SAID FIRST AND SECOND ELECTRODES, SAID VOLTAGE PULSE BEING OF A POLARITY AND AMPLITUDE WHICH WILL CAUSE CURRENT TO FLOW THROUGH SAID SECONDARY WINDING ONLY WHEN SAID SECOND CONTROL SIGNAL VOLTAGE PULSE IS ALSO SUPPLIED TO SAID FIRST AND SECOND ELECTRODES AND THE BIAS ON SAID THIRD ELECTRODE OTHERWISE BEING SUCH THAT CURRENT FLOW THROUGH SAID SECONDARY WINDING IS SUBSTANTIALLY ZERO IN THE ABSENCE OF SAID FIRST CONTROL SIGNAL AND IN THE PRESENCE AND ABSENCE OF SAID SECOND CONTROL SIGNAL VOLTAGE PULSE. 